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Wang2200.org

Although there was excellent upward software compatibility through the various incarnations of the 2200 CPUs, there were in fact three radically different CPU implementations. The fact that there was no "assembly language" exposed by Wang to the public made it possible to make this switcheroo without affecting BASIC/BASIC-2 compatibility. With the extensive history of the family line and my distance from the real history, it is impossible to accurately detail everything without spending a year researching and writing a book. Below is a modest attempt to lay out some of the important details.

Here is an outline of the information on this page:

Wang 2200 Prehistory (link)

By the mid 1960's, Wang started making a name for itself in the electronic calculator business. The LOCI-2 machine lead the way, with the 300 series following up. Simple electronic calculators evolved to be programmable calculators.

In 1968, Wang had acquired Philip Hankins Inc. (PHI). The main asset of PHI was its staff of incredibly smart and talented engineers. Wang started developing two general purpose CPUs. When HP introduced their 9100 programmable calculator, one of these CPUs got re-purposed to be a high end programmable calculator, which became the 700 series. It was wildly successful.

The other PHI-developed computer was the Wang 3300. Aimed squarely at the PDP-8 market, it hosted a time-shared version of BASIC supporting up to 16 users, in theory. Each user was connected to a ASR-33 TTY operating a 10 characters per second. The machine proved difficult to use and didn't sell well, but Wang had learned from the experience.

The next attempt at a CPU was internally called the 800 CPU, and some of the older internal documents reference it, but it ultimately became known as the 2200 CPU.

First Generation 2200 CPU (link)

CPU Model Introduction Comments
2200 A/B May, 1973 [1] CPU and separate power supply
2200 C November, 1974 [2] More microcode features
2200 S/T January, 1975 [3] Integrated power supply; more microcode; cornerstone of WCS family
2200 E/F January, 1976 [4] CPU integrated into terminal housing of the PCS computer

The 2200 project was started in 1970, with Bob Kolk as the project lead. Other key developers were Bruce Patterson, Dave Angel, Joe Wang, and Horace Tsaing. One of the interesting features of the 2200 family was that the CPU wasn't a microprocessor, as the design was begun in 1970 and the first 2200 CPU shipped in April, 1973, predating the introduction of the Intel 8080 (April 1974) and similar micros. Instead the BASIC interpreter was a microcoded affair. No machine language was exposed to the user; although this can be viewed as a shortcoming, it also meant that the implementation could be (and was) radically changed without affecting any user code.

Minimal systems were configured with only 4 KB of RAM, but were upgradable to 32 KB for a hefty premium. The 32 KB RAM limit came about because the internal address registers were 16 bits wide but were nibble addresses, not byte addresses. The BASIC interpreter was in ROM, and different model CPUs have different feature sets included or not. Having BASIC in ROM had some tradeoffs; on the positive side, booting up was instantaneous and it was hard for an errant program to bomb the machine. On the negative side, it was very difficult and expensive for Wang to distribute bug fixes to the BASIC interpreter, so bugs tended not to get fixed.

The 2200 A/B/C series CPUs were identical other than the amount of microcode they contained. The A model had a minimal BASIC, the B model added some more commands and functions, and the C model added a few more commands and functions. The CPU, memory, and I/O cards were spread out on a backplane encased in a sturdy metal box, sometimes likened to a suitcase. Different model variations existed with different numbers of I/O expansion slots. A separate box containing a linear power supply provided the power for the CPU box. The master oscillator ran at 10 MHz and most microinstructions took 16 cycles to complete. RAM was implemented with the very first generation DRAM chips, and microcode ROM was an array of mask programmed chips. It was possible to patch microcode in the field with the addition of a "superpatch" board, basically a small diode array address decoder that could replace a small number of microinstructions.

Due to improvements in TTL density (and probably partially as the result of obsolescence of certain chips) the memory and some of the CPU logic boards were redesigned for the 2200 S/T CPU. The S CPU and T CPU flavors were simply a matter of microcode. The external power supply of the A/B/C models was done away with and an internal linear power supply was used instead. The I/O bus was identical with the A/B/C models. The -T version contained all the possible microcode options and consisted of 20K words of 20b each plus a small "constant" ROM, which totaled 42.5 KB of microcode. Compare that to the 12 KB BASIC in ROM of the TRS-80 Model III that came a few years later.

The final version of the first generation microarchitecture was the E/F CPU. This was a complete repackaging of the 2200 system to make it fit into the housing of a terminal, and was called the PCS (Personal Computer System). Not only was the CPU and memory redesigned, but a number of the I/O controllers too (the I/O controllers from the first generation were not physically compatible with the E/F CPU). The only thing that made this at all possible was that the density of memory and TTL complexity had gotten even higher. The 7055 board was the 2200F backplane and the 7056 board was the 2200E backplane. Although it was possible to load different boards into the backplanes to achieve different configurations, the standard configuration was as follows.

As an indication of the volume of 2200's that Wang shipped, it took from April, 1973 until October 1976 (3.25 years) to produce 10,000 2200 CPUs [5]. That works out to about 12 machines per work day. It made Wang a lot of money, but the volume is certainly low by today's standards.

Trivia: the microcode was mostly written on punched cards that got assembled via an IBM-360 system. [6]

Second Generation 2200 (A.K.A 2600) CPU (link)

CPU Model Introduction Comments
2200 VP September, 1976 [7] New microarchitecture; BASIC-2
2200 MVP March, 1978 [8] Small circuit change; more microcode; new I/O controllers
Micro VP 198x? VLSI implementation of CPU and control logic

The same design team that produced the first generation 2200 also produced the 2nd generation, internally known as the 2600 CPU. One internal memo, from F. Vine and B.(ruce) Patterson, references the 2600 CPU specifications of December 6, 1974. So by late 1974 the 2600 had already been developed pretty far.

The 2600 CPU was a complete redesign, incorporating the latest technology and a much more efficient microarchitecture. Wang BASIC also got a major overhaul with many new features and was dubbed BASIC-2. Despite the complete rewrite and all the new features, BASIC-2 was 99% upwardly compatible with the original Wang BASIC. A BASIC program running on a 2600 CPU was roughly 10x faster than the exact same program running on a 2200T CPU; a factor of 2.5 of that was due to the faster cycle time of the machine, and the other factor of four came from the more powerful microarchitecture instruction set combined with more efficient algorithms. For instance, the square root operation was 25x faster (and more accurate) and the RND operation was 88 times faster (and more random) than that found on the 2200T [9].

One great improvement in the 2600 CPU was that the microcode was no longer stored in ROMs -- it was downloaded from disk on start up, making it much easier to fix bugs in the field. Interestingly, COBOL was developed for the VP CPU and it got as far as running and brochures were sent out, but it never shipped, presumably because Wang decided that that class of customers should instead buy a 2200VS system. BASIC-3 was also announced, but it never shipped. Perhaps part of the problem was the fact that the 32 Kword control store used by the entire VP family wasn't large enough for COBOL and BASIC-3, necessitating a massive field upgrade to a 64 Kword control store.

Although the CPU microarchitecture was entirely incompatible, the I/O structure was kept from the first generation 2200, allowing people to upgrade to the VP without having to throw away all of the their I/O cards and peripherals.

The MVP had the same CPU as the VP and used the same I/O bus. The difference was that the MVP had added a single 30 millisecond one shot timer that the microcode could use to timeslice between different memory partitions, allowing one CPU to service multiple users. Support for cassette I/O was dropped, and rather than having a dedicated CRT and keyboard controller, in their place a multiplexed serial link was used to communicate to the satellite users. Some unused bits of a register were used to provide bank selection to allow supporting a larger RAM (although the per-user maximum was still capped at 56 KB less overhead).

By the early 1980s, Wang was able to reduce the CPU and control logic to a single VLSI chip. This chip interfaced to 32 Kword control RAM (microcode) and a bank of DRAM. Early versions came with 128 KB of DRAM, but later upgrades allowed up to 8 MB of DRAM. (ref: Wang 741-0584-A).

Various versions of the VP and MVP were produced, such as the SVP and LVP, but I believe they were simply packaging changes. VLSI version of the CPU. Clock rates. Internal hard disk. >64 KB RAM.

Trivia: Bruce Patterson and Dave Angel were tired of having to submit punch card decks to the IBM 360 to get their microcode assembled. Instead, for the 2600 project they wrote the microcode development tools (editor, assembler, crossref, disassembler, debugger, firmware simulator) to run on a 32 KB 2200T CPU. [10]

Trivia: The 2200VP was introduced at WESCON in September, 1976. The 6502 was also introduced at that show. This goes to show that although Wang was well aware of microprocessors (they used the 8080 in the terminal multiplexer and in their word processing family), they weren't performance competitive with large boxes full of TTL chips (yet).

Trivia: Wang developed BASIC-3 and COBOL to run on enhanced MVP systems. The enhancement was to max out the control store to 64 Kwords, making it large enough to hold these systems. It isn't clear if they were co-resident. Things went so far as to have training for FAEs to teach them how to upgrade the systems in preparation for the new languages. Then, for whatever reason, Wang decided to release neither BASIC-3 nor COBOL.

Third Generation 2200 CPU (link)

CPU Model Introduction Comments
2200 CS/386 July 1989 [11] Emulation using an 80386 CPU

The 2200 line languished for quite a while with minor improvements along the way. There were enough 2200 systems out in the field that Wang couldn't simply ignore the market, but the development focus was on the VS family. As the installed base of 2200 customers got smaller, the expense of developing new 2200 CPUs couldn't be justified.

Wang took a different approach this time around. The BASIC-2 interpreter was reimplemented to run on an Intel 80386 CPU. A card containing a 386, 256KB of SRAM, 1 to 8 MB of DRAM, and the necessary interface logic was designed. The card plugged into a standard VP-style chassis, replacing any existing CPU and memory cards, but leaving the rest of the system unchanged. This card supported all of the MVP functionality at higher throughput at a better cost profile, and was called the 2200 CS/386. It was introduced by July, 1989.

The CS/386 BASIC-2 interpreter doesn't run on DOS or Windows; instead, just like the VP family, BASIC-2 on the CS/386 is a closed environment. The CS/386 manuals describe the system software has having an incremental compiler [12]. Previous Wang BASIC implementations used simple interpreters; an incremental compiler is a half-way stop between an interpreter and a full compiler. Such a scheme is more complex than a simple interpreter, but has the advantage of being faster. One down side of this is that programs occupy 80% more memory since the original source code and the compiled version are resident in memory at the same time.

The 256KB of fast zero wait-state SRAM was used to hold the BASIC-2 incremental compiler, while the DRAM held the user applications and data. This was a good trade-off since the vast majority of accesses would be to the SRAM.

The first version ran on a 16 MHz 386. In March of 1991, Wang announced a follow-up product called the CS/386 Turbo, consisting of a 32 MHz 386 CPU and up to 32 MB of DRAM, offering twice the performance.

Although it supported the same syntax as the MVP BASIC-2 implementation, the CS/386 version of BASIC-2 didn't always product the exact same answers. For instance, PRINT RND(0),RND(1) would produce the first same number but a different second number. Another example is SELECT D:PRINT ARCSIN(ARCCOS(ARCTAN(TAN(COS(SIN(9)))))). The two implementations give similar but not identical answers. Even the parser is somewhat different. If the user entered 10 DATA 1,2,3,      4,5,6, the MVP BASIC-2 interpreter, like all earlier Wang BASIC interpreters, would preserve the extra spaces. The CS/386 BASIC-2 interpreter would strip the extra spaces.

Footnotes (link)

  1. ⇑ Riding the Runaway Horse, Charles C. Kenney, p. 58
  2. ⇑ Wang Product Guide 700-0787C, Wang Labs,
  3. ⇑ 2200S/2220 BASIC Processing System (700-3493A), Wang Labs,
  4. ⇑ Wang Printout, Vol V, No. 3, Wang Labs, p. 3
  5. ⇑ Wang Printout, Vol VI, No. 1., Wang Labs, p. 5
  6. ⇑ Dave Angel, private communication, email, 1/15/2003
  7. ⇑ Wang Printout, Vol VI, No. 1., Wang Labs, p. 3
  8. ⇑ Wang Printout, Vol VIII, No. 1, Wang Labs, p. 2
  9. ⇑ Dave Angel, private communication, email, 1/14/2003
  10. ⇑ Ibid., 1/15/2003
  11. ⇑ CS/386 Data Sheet (715-2363A), Wang Labs, p. 10
  12. ⇑ Ibid., p. 1